SN74LV8T573
Features
3 Description
- Wide operating range of 1.65V to 5.5V
- 5.5V tolerant input pins
- Single-supply voltage translator (refer to LVx T
Enhanced Input Voltage):
- Up translation:
- 1.2V to 1.8V
- 1.5V to 2.5V
- 1.8V to 3.3V
- 3.3V to 5.0V
- Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
- Up to 150Mbps with 5V or 3.3V VCC
- Supports standard function pinout
- Latch-up performance exceeds 250m A per JESD 17
2 Applications
- Parallel data storage
- Digital bus buffer
The SN74LV8T573 contains eight D-type latches. All channels share a latch enable (LE) input and output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always...
