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SN74AUP1T50 - SCHMITT-TRIGGER BUFFER GATE

Description

The SN74AUP1T50 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in operating.

Features

  • 1.
  • Single-Supply Voltage Translator.
  • Output Level Up to Supply VCC CMOS Level.
  • 1.8 V to 3.3 V (at VCC = 3.3 V).
  • 2.5 V to 3.3 V (at VCC = 3.3 V).
  • 1.8 V to 2.5 V (at VCC = 2.5 V).
  • 3.3 V to 2.5 V (at VCC = 2.5 V.
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity.
  • Ioff Supports Partial Power Down (VCC = 0 V).
  • Very Low Static Power Consumption: 0.1 µA.
  • Very Low Dynamic Power Co.

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Other Datasheets by Texas Instruments

Part Number Description
SN74AUP1T57 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR
SN74AUP1T58 SINGLE-SUPPLY VOLTAGE-LEVEL TRANSLATOR
SN74AUP1T00 POSITIVE-NAND GATE
SN74AUP1T02 POSITIVE-NOR GATE
SN74AUP1T04 INVERTER GATE

Full PDF Text Transcription

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SN74AUP1T50 www.ti.com SCES844A – OCTOBER 2012 – REVISED MARCH 2013 LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE SCHMITT-TRIGGER BUFFER GATE Check for Samples: SN74AUP1T50 FEATURES 1 • Single-Supply Voltage Translator • Output Level Up to Supply VCC CMOS Level – 1.8 V to 3.3 V (at VCC = 3.3 V) – 2.5 V to 3.3 V (at VCC = 3.3 V) – 1.8 V to 2.5 V (at VCC = 2.5 V) – 3.3 V to 2.5 V (at VCC = 2.5 V • Schmitt-Trigger Inputs Reject Input Noise and Provide Better Output Signal Integrity • Ioff Supports Partial Power Down (VCC = 0 V) • Very Low Static Power Consumption: 0.1 µA • Very Low Dynamic Power Consumption: 0.9 µA • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Pb-Free Packages Available: SC-70 (DCK) 2 x 2.1 x 0.65 mm (Height 1.
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