Datasheet4U Logo Datasheet4U.com

SN74AUC2G125 - DUAL BUS BUFFER GATE

Description

This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

Features

  • Available in the Texas Instruments NanoFree™ Package.
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Sub-1-V Operable.
  • Max tpd of 1.8 ns at 1.8 V.
  • Low Power Consumption, 10 μA at 1.8 V.
  • ±8-mA Output Drive at 1.8 V.
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.
  • ESD Protection Exceeds JESD 22.
  • 200.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
SN74101 AND-OR Gate ETC
SN74102 AND Gate ETC
SN74103 Dual J-K Flip-Flop ETC
SN74106 Dual J-K Flip-Flop ETC
SN74108 Dual J-K Flip Flop ETC

Other Datasheets by Texas Instruments

Part Number Description
SN74AUC2G126 DUAL BUS BUFFER GATE
SN74AUC2G00 DUAL 2-INPUT POSITIVE-NAND GATE
SN74AUC2G02 DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G04 DUAL INVERTER GATE
SN74AUC2G06 DUAL INVERTER BUFFER/DRIVER

Full PDF Text Transcription

Click to expand full text
www.ti.com SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES532D – DECEMBER 2003 – REVISED AUGUST 2007 FEATURES • Available in the Texas Instruments NanoFree™ Package • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 1.8 ns at 1.8 V • Low Power Consumption, 10 μA at 1.8 V • ±8-mA Output Drive at 1.
Published: |