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SN74AS109A - Dual J-K Positive-Edge-Triggered Flip-Flop

Description

SN54ALS109A, SN54AS109A .

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Full PDF Text Transcription

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SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL JĆK POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SDAS198B − APRIL 1982 − REVISED AUGUST 1995 • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS109A ′AS109A TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) 50 129 TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 6 29 description SN54ALS109A, SN54AS109A . . . J PACKAGE SN74ALS109A, SN74AS109A . . . D OR N PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q These devices contain two independent J-K positive-edge-triggered flip-flops.
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