Datasheet4U Logo Datasheet4U.com

SN74ALVCH16269 - 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

General Description

This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation.

or demultiplexed from, a single port.

Key Features

  • Member of the Texas Instruments Widebus™ Family.
  • Operates From 1.65 V to 3.6 V.
  • Max tpd of 5 ns at 3.3 V.
  • ±24-mA Output Drive at 3.3 V.
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors.
  • Latch-Up Performance Exceeds 250 mA Per JESD 17.
  • ESD Protection Exceeds JESD 22.
  • 2000-V Human-Body Model (A114-A).
  • 200-V Machine Model (A115-A).

📥 Download Datasheet

Other Datasheets by Texas Instruments

Part Number Description
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER
SN74ALVCH162244 16-BIT BUFFER/DRIVER
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER
SN74ALVCH162373 16-BIT TRANSPARENT D-TYPE LATCH
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74ALVCH16240 16-BIT BUFFER/DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.ti.com FEATURES • Member of the Texas Instruments Widebus™ Family • Operates From 1.65 V to 3.6 V • Max tpd of 5 ns at 3.3 V • ±24-mA Output Drive at 3.3 V • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.