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SN74ALS164A - 8-Bit Parallel-Out Serial Shift Register

Description

QC 5 QD 6 10 QE 9 CLR This 8-bit parallel-out serial shift register

Features

  • GND 7 8 CLK AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided that the minimum setup-time requiremen.

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Full PDF Text Transcription

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SN74ALS164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą SDAS159D − APRIL 1982 − REVISED DECEMBER 1994 • AND-Gated ( Enable/Disable) Serial Inputs • Fully Buffered Clock and Serial Inputs D OR N PACKAGE (TOP VIEW) • Direct Clear • Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs A1 B2 QA 3 QB 4 14 VCC 13 QH 12 QG 11 QF description QC 5 QD 6 10 QE 9 CLR This 8-bit parallel-out serial shift register features GND 7 8 CLK AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse.
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