Download SN65LVDS93 Datasheet PDF
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SN65LVDS93 Key Features

  • 28:4 Data Channel pression at up to 1.904 Gigabits per Second Throughput
  • Suited for Point-to-Point Subsystem munication With Very Low EMI
  • 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential
  • Selectable Rising or Falling Clock Edge Triggered Inputs
  • Bus Pins Tolerate 6-kV HBM ESD
  • Operates From a Single 3.3-V Supply and
  • 5-V Tolerant Data Inputs
  • Packaged in Thin Shrink Small-Outline
  • Consumes <1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range

SN65LVDS93 Description

The SN65LVDS93 LVDS serdes (serializer/ deserializer) transmitter contains four 7-bit parallelload serial-out shift registers, a 7‫נ‬clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a patible receiver, such as the...