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SN65LVDS93 - LVDS SERDES TRANSMITTER

Description

The SN65LVDS93 LVDS serdes (serializer/ deserializer) transmitter contains four 7-bit parallelload serial-out shift registers, a 7‫נ‬clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit.

Features

  • 1.
  • 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput.
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI.
  • 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential.
  • Selectable Rising or Falling Clock Edge Triggered Inputs.
  • Bus Pins Tolerate 6-kV HBM ESD.
  • Operates From a Single 3.3-V Supply and 250 mW (Typ).
  • 5-V Tolerant Data Inputs.
  • P.

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Full PDF Text Transcription

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SN65LVDS93 www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009 LVDS SERDES TRANSMITTER FEATURES 1 • 28:4 Data Channel Compression at up to 1.904 Gigabits per Second Throughput • Suited for Point-to-Point Subsystem Communication With Very Low EMI • 28 Data Channels Plus Clock in Low-Voltage TTL and 4 Data Channels Plus Clock Out Low-Voltage Differential • Selectable Rising or Falling Clock Edge Triggered Inputs • Bus Pins Tolerate 6-kV HBM ESD • Operates From a Single 3.
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