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SN54LV126A - Quadruple Bus Buffer Gate

Datasheet Summary

Description

The ‘LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs.

Features

  • 1 2-V to 5.5-V VCC Operation.
  • Max tpd of 6.5 ns at 5 V.
  • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C.
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection.
  • Support Mixed-Mode Voltage Operation on All Ports.
  • Latch-Up Performance Exceeds 250 mA per JESD 17.
  • ESD Protection Exceeds JESD 22.
  • 2000-V H.

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Datasheet preview – SN54LV126A

Datasheet Details

Part number SN54LV126A
Manufacturer Texas Instruments
File Size 1.02 MB
Description Quadruple Bus Buffer Gate
Datasheet download datasheet SN54LV126A Datasheet
Additional preview pages of the SN54LV126A datasheet.

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Full PDF Text Transcription

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54LV126A, SN74LV126A SCES131I – MARCH 1998 – REVISED FEBRUARY 2015 SNx4LV126A Quadruple Bus Buffer Gates With 3-State Outputs 1 Features •1 2-V to 5.5-V VCC Operation • Max tpd of 6.5 ns at 5 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.
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