Click to expand full text
www.ti.com
FEATURES
1
• Synchronous Parallel Load • Positive-Edge-Triggered Clocking • J and K Inputs to First Stage • Complementary Outputs From Last Stage • Package Options: Plastic and Ceramic DIPS
and Ceramic Chip Carriers • Dependable Texas lnstruments Quality and
Reliability
DESCRIPTION/ORDERING INFORMATION
These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).
Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input.
SN54HC195 Datasheet
