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SN54F283J - 4-Bit Binary Full Adders

Download the SN54F283J datasheet PDF. This datasheet also covers the SN54F283 variant, as both devices belong to the same 4-bit binary full adders family and are provided as variant models within a single manufacturer datasheet.

Description

The ′F283 is a full adder that performs the addition of two 4-bit binary words.

The sum (Σ) outputs are provided for each bit and the resultant carry (C4) output is obtained from the fourth bit.

Features

  • full internal look-ahead across all four bits generating the carry term C4 in typically 5.7 ns. This capability provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form. End-around carry can be accomplished without the need for logic or level inversion. The ′F283 can be used with either all-active-high (positive logic) or all-active-low (negativ.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN54F283-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
SN54F283 4-Bit Binary Full Adders
SN54F280B 9-Bit Parity Generators/Checkers
SN54F20 DUAL 4-INPUT POSITIVE-NAND GATES
SN54F21 Dual 4-Input Positive-AND Gates
SN54F240 OCTAL BUFFERS/DRIVERS

Full PDF Text Transcription

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• Full-Carry Look-Ahead Across the Four Bits • Systems Achieve Partial Look-Ahead Performance With the Economy of Ripple Carry • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description The ′F283 is a full adder that performs the addition of two 4-bit binary words. The sum (Σ) outputs are provided for each bit and the resultant carry (C4) output is obtained from the fourth bit. The device features full internal look-ahead across all four bits generating the carry term C4 in typically 5.7 ns. This capability provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation.
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