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D Processed to MIL-PRF-38535 (QML)
D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU
-- Object Compatible With the TMS320C2xx Family
-- Source Code Compatible With SMJ320C25
-- Upwardly Compatible With SMJ320C50 -- 50-ns Instruction Cycle Time
D Memory
-- 544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM
-- 16K Words × 16 Bits of On-Chip Program Flash EEPROM
-- 224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space)
D Event-Manager Module
-- 12 Compare/Pulse-Width Modulation (PWM) Channels
-- Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Upand Up/Down Counting
-- Three 16-Bit Full-Compare Units With Deadband
-- Three 16-Bit Simple-Compare Units -- Four Capture Units (T
SMJ320F240 Datasheet
