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CY74FCT16500T - 18-Bit Registered Transceivers

Description

These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs.

Features

  • FCT-C speed at 4.6 ns.
  • Ioff supports partial-power- mode operation.
  • Edge-rate control circuitry for significantly improved noise characteristics.
  • Typical output skew < 250 ps.
  • ESD > 2000V.
  • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages.
  • Industrial temperature range of.
  • 40˚C to +85˚C.
  • VCC = 5V ± 10% CY74FCT16500T Features:.
  • 64 mA sink current, 32 mA source current.
  • Typical VOLP (ground bounc.

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Full PDF Text Transcription

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Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16500T CY74FCT162500T SCCS056A - August 1994 - Revised October 2001 Features • FCT-C speed at 4.6 ns • Ioff supports partial-power- mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of −40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16500T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C CY74FCT162500T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.
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