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CDCP1803 - 1:3 LVPECL CLOCK BUFFER

Datasheet Summary

Description

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution.

The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

Features

  • 1.
  • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs.
  • Programmable Output Divider for Two LVPECL Outputs.
  • Low-Output Skew 15 ps (Typical).
  • VCC Range 3 V.
  • 3.6 V.
  • Signaling Rate Up to 800-MHz LVPECL.
  • Differential Input Stage for Wide CommonMode Range.
  • Provides VBB Bias Voltage Output for SingleEnded Input Signals.
  • Receiver Input Threshold ±75 mV.
  • 24-Terminal QFN Package (4 mm ×.

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Datasheet preview – CDCP1803

Datasheet Details

Part number CDCP1803
Manufacturer Texas Instruments
File Size 2.07 MB
Description 1:3 LVPECL CLOCK BUFFER
Datasheet download datasheet CDCP1803 Datasheet
Additional preview pages of the CDCP1803 datasheet.

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Full PDF Text Transcription

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www.ti.com CDCP1803 SCAS727F – NOVEMBER 2003 – REVISED DECEMBER 2013 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER Check for Samples: CDCP1803 FEATURES 1 • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs • Programmable Output Divider for Two LVPECL Outputs • Low-Output Skew 15 ps (Typical) • VCC Range 3 V–3.
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