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CDC857-3 - 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS

This page provides the datasheet information for the CDC857-3, a member of the CDC857-2 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS family.

Description

The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

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Datasheet preview – CDC857-3

Datasheet Details

Part number CDC857-3
Manufacturer Texas Instruments
File Size 155.46 KB
Description 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
Datasheet download datasheet CDC857-3 Datasheet
Additional preview pages of the CDC857-3 datasheet.

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Full PDF Text Transcription

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CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM DGG PACKAGE (TOP VIEW) Applications D Distributes One Differential Clock Input to Ten Differential Outputs D External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Clock Input D Operates at VCC = 2.5 V and AVCC = 3.
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