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CDC3RL02 - Low Phase-Noise Two-Channel Clock Fan-Out Buffer

Description

The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities.

Features

  • Low Additive Noise:.
  • 149 dBc/Hz at 10-kHz Offset Phase Noise.
  • 0.37 ps (RMS) Output Jitter.
  • Limited Output Slew Rate for EMI Reduction (1- to 5-ns Rise/Fall Time for 10-pF to 50-pF Loads).
  • Adaptive Output Stage Controls Reflection.
  • Regulated 1.8-V Externally Available I/O Supply.
  • Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP (0.8 mm × 1.6 mm).
  • ESD Performance Exceeds JESD 22.
  • 2000-V Human-Body Model (A114-A).

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Datasheet preview – CDC3RL02

Datasheet Details

Part number CDC3RL02
Manufacturer Texas Instruments
File Size 935.69 KB
Description Low Phase-Noise Two-Channel Clock Fan-Out Buffer
Datasheet download datasheet CDC3RL02 Datasheet
Additional preview pages of the CDC3RL02 datasheet.

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Full PDF Text Transcription

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CDC3RL02 SCHS371G – NOVEMBER 2009 – REVISED NOVEMBER 2022 CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer 1 Features • Low Additive Noise: – –149 dBc/Hz at 10-kHz Offset Phase Noise – 0.37 ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1- to 5-ns Rise/Fall Time for 10-pF to 50-pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8-V Externally Available I/O Supply • Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP (0.8 mm × 1.
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