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CD54HC195 - 4-Bit Parallel Access Register

General Description

Asynchronous Master Reset J, K, (D) Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfer Shift Right and Parallel Load Capability Complementary Output From Last Stage Buffered Inputs CTyLp=ic1a5l pfMF,ATXA==52

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data sheet acquired from Harris Semiconductor SCHS165E September 1997 - Revised October 2003 CD54HC195, CD74HC195 High-Speed CMOS Logic 4-Bit Parallel Access Register [ /Title (CD74 HC195 ) /Subject (High Speed CMOS Logic 4-Bit Parallel Access Register) /Autho Features Description • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • CTyLp=ic1a5l pfMF,ATXA==5205MoHCz at VCC = 5V, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . .