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54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A – JANUARY 1991 – REVISED APRIL 1996
D Members of the Texas Instruments
Widebus™ Family
D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
description
The ’ACT16657 contain two noninverting octal transceiver sections with separate parity generator/checker circuits