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74ACT11543 - OCTAL REGISTERED TRANSCEIVER

Description

This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction.

Separate latch enable (LEAB or LEBA) and output enable (GAB or GBA) inputs are provided for each register to permit independent control in either direction of data flow.

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74ACT11544 OCTAL REGISTERED TRANSCEIVER
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Full PDF Text Transcription

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74ACT11543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCAS136 – D3608, JULY 1990 – REVISED APRIL 1993 • Inputs Are TTL-Voltage Compatible • 3-State True Outputs • Back-to-Back Registers for Storage • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise t• EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process • 500-mA Typical Latch-Up Immunity at 125°C description This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch enable (LEAB or LEBA) and output enable (GAB or GBA) inputs are provided for each register to permit independent control in either direction of data flow.
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