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74ACT11074 - DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Description

This device contains two independent positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs.

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Full PDF Text Transcription

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74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 D Inputs Are TTL-Voltage Compatible D Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise D EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N) D, DB, OR N PACKAGE (TOP VIEW) 1PRE 1 1Q 2 1Q 3 GND 4 2Q 5 2Q 6 2PRE 7 14 1CLK 13 1D 12 1CLR 11 VCC 10 2CLR 9 2D 8 2CLK description This device contains two independent positive-edge-triggered D-type flip-flops.
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