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74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)
description
SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996
D OR N PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A 10 3B
9 4A
This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function Y = A ⊕ B = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output.
74AC11086 Datasheet
