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XPLA3 - CPLD

Features

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  • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility Based on industry's first TotalCMOS™ PLD - both CMOS design and process technologies Advanced 0.35µ five metal layer E2CMOS process - 1,000 erase/program cycles guaranteed - 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface - Full Boundary Scan Test.

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APPLICATION NOTE 0  CoolRunner™ XPLA3 CPLD Advance Product Specification DS012 (v1.1) March 3, 2000 0 14* Features • • • • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility Based on industry's first TotalCMOS™ PLD - both CMOS design and process technologies Advanced 0.35µ five metal layer E2CMOS process - 1,000 erase/program cycles guaranteed - 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface - Full Boundary Scan Test (IEEE 1149.
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