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APPLICATION NOTE
DS041 (v1.2) August 10, 2000
Features
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Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed IEEE 1149.1-compliant, JTAG Testing Capability - Four pin JTAG interface (TCK, TMS, TDI, TDO) - IEEE 1149.1 TAP Controller - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ 5V, In-System Programmable (ISP) using the JTAG interface - On-chip supervoltage generation - ISP commands include: Enable, Erase, Program, Verify - Supported by multiple ISP programming platforms High speed pin-to-pin delays of 7.