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XCF01S - Platform Flash In-System Programmable Configuration PROMS

Download the XCF01S datasheet PDF. This datasheet also covers the XCF01SVO20C variant, as both devices belong to the same platform flash in-system programmable configuration proms family and are provided as variant models within a single manufacturer datasheet.

Features

  • In-System Programmable PROMs for Configuration of Xilinx® FPGAs.
  • Low-Power Advanced CMOS NOR Flash Process.
  • Endurance of 20,000 Program/Erase Cycles.
  • Operation over Full Industrial Temperature Range (.
  • 40°C to +85°C).
  • IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing.
  • JTAG Command Initiation of Standard FPGA Configuration.
  • Cascadable for Storing Longer or Multiple Bitstreams.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (XCF01SVO20C_Xilinx.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number XCF01S
Manufacturer Xilinx (now AMD)
File Size 444.25 KB
Description Platform Flash In-System Programmable Configuration PROMS
Datasheet download datasheet XCF01S Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by Xilinx (now AMD)

Part Number Description
XCF02S Platform Flash In-System Programmable Configuration PROMs
XCF04S Platform Flash In-System Programmable Configuration PROMs
XCF08P Platform Flash In-System Programmable Configuration PROMs
XCF16P Platform Flash In-System Programmable Configuration PROMs
XCF16S Platform Flash In-System Programmable Configuration PROMS

Full PDF Text Transcription

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35 R DS123 (v2.19) June 6, 2016 Platform Flash In-System Programmable Configuration PROMs Product Specification Features • In-System Programmable PROMs for Configuration of Xilinx® FPGAs • Low-Power Advanced CMOS NOR Flash Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) • IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing • JTAG Command Initiation of Standard FPGA Configuration • Cascadable for Storing Longer or Multiple Bitstreams • Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ) • I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V • Design Support Using the Xilinx ISE® Alliance and Foundation™ Software Packages • XCF01S/XCF02S/XCF04S • 3.
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