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XC9572XL - High Performance CPLD

Description

cations and computing systems.

It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns.

See Figure 2 for overview.

Features

  • 5 ns pin-to-pin logic delays.
  • System frequency up to 178 MHz.
  • 72 macrocells with 1,600 usable gates.
  • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) - Pb-free available for all packages.
  • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.

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Other Datasheets by Xilinx (now AMD)

Part Number Description
XC9572 XC9572 In-System Programmable CPLD
XC9500XL High-Performance CPLD
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Full PDF Text Transcription

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0 R XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 72 macrocells with 1,600 usable gates • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.
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