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9
1
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XC9536 In-System Programmable CPLD
1 1*
December 4, 1998 (Version 5.0)
Product Specification
Features
• • • • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.