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XC95216 In-System Programmable CPLD
1 0*
August 21, 2001 (Version 3.1)
Product Specification
Features
• • • • • 10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.