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Application Note: CoolRunner-II CPLD
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Implementing Keypad Scanners with CoolRunner-II
XAPP512 (v1.0) April 4, 2005
Summary
This application note provides a functional description of Verilog source code for a keypad scanner. The code is used to target the lowest density, 32-macrocell CoolRunnerTM-II XC2C32A CPLD device in a CP56 package (6 mm x 6 mm). The keypad accommodated in this design has 8 rows and 8 columns. The design can easily be scaled to target keypads with more or less rows/columns. For instance, a keypad with 7 rows and 7 columns would allow the design to fit in the smallest QFG32 package (5 mm x 5 mm). To obtain the Verilog source code described in this document, see “Verilog Code,” page 4, for instructions.