Datasheet4U Logo Datasheet4U.com

W942516AH - DDR SDRAM

General Description

W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words × 4 banks × 16 bits.

Using pipelined architecture and 0.175 µm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).

Key Features

  • 2.5V ± 0.2V Power Supply.
  • Up to 143 MHz Clock Frequency.
  • Double Data Rate architecture; two data transfers per clock cycle.
  • Differential clock inputs (CLK and CLK ).
  • DQS is edge-aligned with data for Read; center-aligned with data for Write.
  • CAS Latency: 2 and 2.5.
  • Burst Length: 2, 4, and 8.
  • Auto Refresh and Self Refresh.
  • Precharged Power Down and Active Power-Down.
  • Write Data Mask.
  • Write Latency.

📥 Download Datasheet

Other Datasheets by Winbond

Part Number Description
W942516CH DDR SDRAM
W942508CH DDR SDRAM
W9425G6DH 4M X 4 BANKS X 16 BITS DDR SDRAM
W9425G6EH 4M X 4 BANKS X 16 BITS DDR SDRAM
W9425G6JB 4M x 4-BANKS x 16-BITS DDR SDRAM
W9425G6JH 4M X 4 BANKS X 16 BITS DDR SDRAM
W9425G6KH 4-M x 4-BANKS 16-BITS DDR SDRAM
W9425G8EH 8M X 4 BANKS X 8 BITS DDR SDRAM
W9412G2CB 1M X 4 BANKS X 32 BITS GDDR SDRAM
W9412G2IB 1M X 4 BANKS X 32 BITS GDDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PRELIMINARY W942516AH 4M × 4 BANKS × 16 BIT DDR SDRAM GENERAL DESCRIPTION W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the 75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2 specification All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE).