Description
I/O0-31
56
Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select
A0-18 SWE1-4# SCS# OE# VCC GND NC FWE1-4# FCS#
Block Diagram
FWE2# SWE2# FWE3# SWE3# FWE4# SWE4#
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
512K x 8 Flash 512K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
May 2006 Rev.9
1
White Electronic Designs Corporation
(602) 4
Features
- Access Times of 25ns (SRAM) and 70, 90ns (FLASH) Packaging.
- 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic HIP (Package 402).
- 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height. Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Figure 2). Package to be developed. 512Kx32 SRAM 512Kx32 5V Flash Organized as 512Kx32 of SRAM and 512Kx32 of Flash Memory with common Data Bus Low Power CMOS Commercial, Industrial and Military Temperature.
WSF512K32-XXX Datasheet
