Datasheet4U Logo Datasheet4U.com

SI7945DP - Dual P-Channel 30-V (D-S) MOSFET

Description

The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS.

55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive.

📥 Download Datasheet

Datasheet preview – SI7945DP

Datasheet Details

Part number SI7945DP
Manufacturer Vishay
File Size 202.92 KB
Description Dual P-Channel 30-V (D-S) MOSFET
Datasheet download datasheet SI7945DP Datasheet
Additional preview pages of the SI7945DP datasheet.

📁 Similar Datasheet

  • SI7946DP - Dual N-Channel 150-V (D-S) MOSFET (Vishay Siliconix)
  • Si7904DN - Thermoelectric Cooler Controller (Analog Devices)
  • SI7905 - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7905A - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7906 - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7906A - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7908 - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7908A - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7909 - 3-Terminal Negative Voltage Regulator (SeCoS)
  • SI7909DN - Dual P-Channel 12-V (D-S) MOSFET (Vishay Siliconix)
Other Datasheets by Vishay
  • SI7940DP - Dual N-Channel 12-V (D-S) MOSFET
  • SI7941DP - Dual P-Channel 30-V (D-S) MOSFET
  • SI7942DP - Dual N-Channel 100-V (D-S) MOSFET
  • SI7943DP - Dual P-Channel 30-V (D-S) MOSFET
  • SI7948DP - Dual N-Channel 60-V (D-S) MOSFET
  • Si7949DP - Dual P-Channel 60-V (D-S) MOSFET
  • SI7900AEDN - Dual N-Channel MOSFET
  • SI7900EDN - Dual N-Channel 20-V (D-S) MOSFET - Common Drain

Full PDF Text Transcription

Click to expand full text
SPICE Device Model Si7945DP www.DataSheet4U.com Vishay Siliconix Dual P-Channel 30-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.
Published: |