VT83205
Description
The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30p F (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs SO:S2 are used for frequency and output selection.
Features
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- = 3.3V supply operation Packaged in 16-pin SOIC & QSOP packages. Replaces separate VCXO and multiplier Uses inexpensive pullable crystal
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- = On-chip VCXO with 200 ppm pull range (±100 ppm) 5V-tolerant control inputs Zero ppm synthesis error in both clocks
Figure 1. Functional Block Diagram
VDD1
VDD2
VIN X2
Load Cap Control Output Buffer osc Low Phase Noise PLL Output Buffer X1 S2:S0 OE CLK2 CLK1
10-14 MHz Pullable Crystal
Load Caps
2001-03-08 Vaishali Semiconductor
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