Datasheet4U Logo Datasheet4U.com

TC74VCX245FK - Low-Voltage Octal Bus Transceiver

General Description

2.

The TC74VCX245FK is a high performance CMOS octal bus transceiver which is guaranteed to operate from 1.2 V to 3.6 V.

Key Features

  • (Note) (1) Low-voltage operation: VCC = 1.2 to 3.6 V (2) High-speed operation: tpd = 3.5 ns (max) (VCC = 3.0 to 3.6 V) tpd = 4.2 ns (max) (VCC = 2.3 to 2.7 V) tpd = 8.4 ns (max) (VCC = 1.65 to 1.95 V) tpd = 16.8 ns (max) (VCC = 1.4 to 1.6 V) tpd = 42.0 ns (max) (VCC = 1.2 V) (3) Output current: IOH/IOL = ±24 mA (min) (VCC = 3.0 V) IOH/IOL = ±18 mA (min) (VCC = 2.3 V) IOH/IOL = ±6 mA (min) (VCC = 1.65 V) IOH/IOL = ±2 mA (min) (VCC = 1.4 V) (4) Latch-up performance: -300 mA (5) ESD performance: Hu.

📥 Download Datasheet

Datasheet Details

Part number TC74VCX245FK
Manufacturer Toshiba
File Size 251.13 KB
Description Low-Voltage Octal Bus Transceiver
Datasheet download datasheet TC74VCX245FK Datasheet

Other Datasheets by Toshiba

Part Number Description
TC74VCX245FT Low-Voltage Octal Bus Transceiver
TC74VCX244FK Low-Voltage Octal Bus Buffer
TC74VCX244FT Low-Voltage Octal Bus Buffer
TC74VCX2125FT Low-Voltage Quad Bus Buffer
TC74VCX2244FK Low-Voltage Octal Bus Buffer
TC74VCX2244FT Low-Voltage Octal Bus Buffer
TC74VCX2373FK Low-Voltage Octal D-Type Latch
TC74VCX2373FT Low-Voltage Octal D-Type Latch
TC74VCX2374FK Low-Voltage Octal D-Type Flip-Flop
TC74VCX2374FT Low-Voltage Octal D-Type Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Digital Integrated Circuits Silicon Monolithic TC74VCX245FK TC74VCX245FK 1. Functional Description • Low-Voltage Octal Bus Transceiver with 3.6-V Tolerant Inputs and Outputs 2. General The TC74VCX245FK is a high performance CMOS octal bus transceiver which is guaranteed to operate from 1.2 V to 3.6 V. Designed for use in 1.5 V, 1.8 V, 2.5 V or 3.3 V systems, it achieves high speed operation while maintaining the CMOS low power dissipation. It is also designed with over voltage tolerant inputs and outputs up to 3.6 V. The direction of data transmission is determined by the level of the DIR inputs. The OE inputs can be used to disable the device so that the busses are effectively isolated. All inputs are equipped with protection circuits against static discharge. 3.