Download the TC74HC126AP datasheet PDF.
This datasheet also covers the TC74HC125AP variant, as both devices belong to the same quad bus buffer family and are provided as variant models within a single manufacturer datasheet.
Key Features
High speed: tpd = 10 ns (typ. ) at VCC = 5 V.
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
High noise immunity: VNIH = VNIL = 28% VCC (min).
Output drive capability: 15 LSTTL loads.
Symmetrical output impedance: |IOH| = IOL = 6 mA (min).
Balanced propagation delays: tpLH ∼.
tpHL.
Wide operating voltage range: VCC (opr) = 2 to 6 V.
Pin and function compatible with 74LS125/126
TC74HC125AP, TC74HC126AP TC74HC1.
Full PDF Text Transcription for TC74HC126AP (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
TC74HC126AP. For precise diagrams, and layout, please refer to the original PDF.
HC125AF TC74HC126AP, TC74HC126AF TC74HC125AP/AF TC74HC126AP/AF Quad Bus Buffer Quad Bus Buffer The TC74HC125A/126A are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC125A requires the 3-state control input G to be set high to place the output into the high impedance state, whereas the TC74HC126A requires the control input to be set low to place the output into high impedance. All inputs are equipped with protection circuits against static discharge or transient exces
TC74HC126AP Datasheet
