SEG04G72B1BC2MT-30R - SDRAM registered SO-RDIMM

Datasheet Summary

Features

200 Pin SO-RDIMM SEG04G72B1BC2MT-30R 4GByte in FBGA Technology RoHS compliant.
200-pin 72-bit Small Outline Registered Dual-In-Line Double Data Rate Synchronous DRAM Module Module organization: dual rank 512Mx72 VDD = 1.8V +0.1V, VDDQ = 1.8V +0.1V 1.8V I/O ( SSTL_18 compatible) Serial Presence Detect with EEPROM Phase-lock loop (PLL) clock driver to reduce loading Supports ECC error detection and correction Gold-contact pad This module family.

Swissbit

📥 Download Datasheet

Datasheet Details

Part number	SEG04G72B1BC2MT-30R
Manufacturer	Swissbit
File Size	582.12 KB
Description	SDRAM registered SO-RDIMM
Datasheet	SEG04G72B1BC2MT-30R Datasheet
Additional preview pages of the SEG04G72B1BC2MT-30R datasheet.

📁 Similar Datasheet

SEG10FG - Surface-Mount Standard Rectifiers (Vishay)
SEG8R5N06AGH - Silicon N-Channel MOSFET (Winsemi)
SEG9296AGH - Silicon N-Channel MOSFET (Winsemi)
SEGC10DH - High Efficient Rectifier (Zowie Technology)
SEGC10GH - High Efficient Rectifier (Zowie Technology)
SEGC10JH - High Efficient Rectifier (Zowie Technology)
SEGC10KH - High Efficient Rectifier (Zowie Technology)
SEGC10MH - High Efficient Rectifier (Zowie Technology)

Other Datasheets by Swissbit

Full PDF Text Transcription

Click to expand full text

preliminary Data Sheet Rev.0.9 07.01.2013 4GB DDR2 – SDRAM registered SO-RDIMM Features: 200 Pin SO-RDIMM SEG04G72B1BC2MT-30R 4GByte in FBGA Technology RoHS compliant          200-pin 72-bit Small Outline Registered Dual-In-Line Double Data Rate Synchronous DRAM Module Module organization: dual rank 512Mx72 VDD = 1.8V +0.1V, VDDQ = 1.8V +0.1V 1.8V I/O ( SSTL_18 compatible) Serial Presence Detect with EEPROM Phase-lock loop (PLL) clock driver to reduce loading Supports ECC error detection and correction Gold-contact pad This module family is fully pin and functional compatible to the JEDEC PC2-5300 spec. and JEDEC- Standard MO 224. (see www.jedec.

Published: Oct 13, 2014 |