ST2317S23RG
DESCRIPTION
ST2317S23RG is the P-Channel logic enhancement mode power field effect transistor is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other battery powered circuits where high-side switching and low in-line power loss are required in a very small outline surface mount package.
PIN CONFIGURATION SOT-23-3L
1.Gate 2.Source 3.Drain
PART MARKING SOT-23-3L
17YW
Y: Year Code W: Week Code
FEATURE l -40V/-5.0A, RDS(ON) = 37mΩ (Typ.) @VGS = -10V l -40V/-3.0A, RDS(ON) = 51mΩ @VGS = -4.5V l Super high density cell design for extremely low RDS(ON) l Exceptional on-resistance and maximum DC current capability l SOT-23 package design
STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech.
ST2317S23RG 2016...
