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CXK77P36E160GB - 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

Download the CXK77P36E160GB datasheet PDF. This datasheet also covers the CXK variant, as both devices belong to the same 16mb lw r-l hstl high speed synchronous srams (512k x 36 or 1m x 18) family and are provided as variant models within a single manufacturer datasheet.

Description

The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins.

Features

  • 4 Speed Bins -4 (-4A) (-4B) -42 (-42A) (-42B) -43 (-43A) (-43B) -44 Cycle Time / Access Time 4.0ns / 3.9ns (3.8ns) (3.7ns) 4.2ns / 4.2ns (4.1ns) (4.0ns) 4.3ns / 4.5ns (4.4ns) (4.3ns) 4.4ns / 4.7ns.
  • Single 3.3V power supply (VDD): 3.3V ± 5% Dedicated output supply voltage (VDDQ): 1.9V typical HSTL-compatible I/O interface with dedicated input refer.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CXK-77P.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Sony Semiconductor Solutions

Part Number Description
CXK77P18E160GB 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77B1810AGB High Speed Bi-CMOS Synchronous Static RAM
CXK77B1810AGB-5 High Speed Bi-CMOS Synchronous Static RAM
CXK77B1810AGB-6 High Speed Bi-CMOS Synchronous Static RAM
CXK77B3610GB-6 High Speed Bi-CMOS Synchronous Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SONY® CXK77P36E160GB / CXK77P18E160GB 4/42/43/44 Preliminary 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) 8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18) Description The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Two distinct R-L modes of operation are supported, selectable via the M2 mode pin.
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