Datasheet4U Logo Datasheet4U.com

82S25 - 64-BIT BIPOLAR SCRATCH PAD MEMORY

General Description

The 82S25 is a 64-bit, Schottky clamped TTL, ReadWrite Random Access Memory ideal for use in scratch pad and high-speed buffer memory applications.

The 82S25 is a fu lIy decoded memory array organ ized as 16 words of 4 bits each, with separate input and output lines.

Key Features

  • PNP inputs, one chip enable line, and open collector outputs for ease of memory expansion. The outputs of the 82S25 assume a logic "1" state during write. This allows both memory inputs and outputs to share a common bus for minimizing interconnections, and more effective utilization of common I/O circuitry. The 82S25 is available in the commercial and military temperature ranges. For the commercial temperature range (DOC to +75°C) specify N82S25, B or F. For the military temperature range (-55°C.

📥 Download Datasheet

Datasheet Details

Part number 82S25
Manufacturer Signetics
File Size 157.03 KB
Description 64-BIT BIPOLAR SCRATCH PAD MEMORY
Datasheet download datasheet 82S25 Datasheet

Other Datasheets by Signetics

Part Number Description
82S21 64-BIT BIPOLAR HIGH SPEED WRITE-WHILE-READ RAM
82S212 2304-Bit Bipolar Ram
82S214 2048-BIT BIPOLAR ROM
82S215 4096-BIT BIPOLAR ROM
82S226 1024-BIT BIPOLAR READ ONLY MEMORY
82S229 1024-BIT BIPOLAR READ ONLY MEMORY
82S23 256-BIT BIPOLAR PROGRAMMABLE ROM
82S230 2048-BIT BIPOLAR ROM
82S231 2048-BIT BIPOLAR ROM
82S27 1024-BIT BIPOLAR PROGRAMMABLE ROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Si!l0otiCS 82S25 64-BIT BIPOLAR SCRATCH PAD MEMORY (16x4 RAM) FEBRUARY 1975 DIGITAL 8000 SERIES TTL/MEMORY DESCRIPTION The 82S25 is a 64-bit, Schottky clamped TTL, ReadWrite Random Access Memory ideal for use in scratch pad and high-speed buffer memory applications. The 82S25 is a fu lIy decoded memory array organ ized as 16 words of 4 bits each, with separate input and output lines. It features PNP inputs, one chip enable line, and open collector outputs for ease of memory expansion. The outputs of the 82S25 assume a logic "1" state during write. This allows both memory inputs and outputs to share a common bus for minimizing interconnections, and more effective utilization of common I/O circuitry. The 82S25 is available in the commercial and military temperature ranges.