74S200
DESCRIPTION
The 54/74S200/201 and 54/74S301 are Schottky clamped TTL, read/write memory arrays organized as 256 words of one bit each. They feature either open collector or tri-state outputs options for optimization of word expansion in bussed organizations. Memory expansion is further enhanced by full on-chip address decoding, three chip enable inputs and PNP input transistors wh ich reduce input loading to 25IJA for a "1" level and -250IJA (S54S200/201/301) or -100IJA (N74S2001201/301) for a "0" level.
The additional feature of output blanking during write (DO terminal "H" or "Hi-Z" state) permits DO and DIN terminals to share a mon I/O line to reduce system interconnections. Both devices have fast read access and write cycle times and thus are ideally suited in high speed memory applications such as "Cache", buffers, scratch pads, writable control stores, etc.
Both devices are available in the mercial and military temperature ranges. For the mercial temperature range (O°C to +75°C)...
