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HYS64V8000GU - 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

Description

A0-A11 BA0,BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 CLK0, CLK1 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C.

Features

  • tion time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown. tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD tT + 1.4 V 50 Ohm INPUT 1.4V Z=50 Ohm I/O tAC tLZ tOH tAC 50 pF OUTPUT 1.4V tHZ fig.1 5. If clock rising time is lon.

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Other Datasheets by Siemens Semiconductor Group (now Infineon)

Part Number Description
HYS64V8000GU-10 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module
HYS64V8200GU-10 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS64V8200GU-8 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS64V8200GU-8B 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
HYS64V8220GU-10 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module

Full PDF Text Transcription

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3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules HYS64V8000GU-10 HYS72V8000GU-10 • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications 1 bank 8M x 64, 8M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatible JEDEC standard Synchronous DRAMs (SDRAM) Performance: -10 fCK tAC Max. Clock frequency Max. access time from clock 66 MHz @ CL=2 100 MHz @ CL=3 8 ns @ CL=2 7 ns @ CL=3 • • • • • • • Single +3.3V(± 0.
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