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PEB24902 - Quad IEC AFE

Description

of ADC and table 5, ADC Fig.

Edition 5.96 This edition was realized using the software system FrameMaker®.

Siemens AG 1995.

Features

  • MOS Digital to Analogue conversion (transmit pulse) Output buffering Analogue to digital conversion Detection of signal on the line Master clock generation by PLL P-MQFP-64 Package Compliant to ANSI T1.601 (1992), ETSI ETR 080 (1995).
  • JTAG boundary scan path compliant to IEEE 1149.1 P-MQFP-64-1 Semiconductor Group 6 05.96 PEB 24902 PEF 24902 Overview 1.2 Logic Symbol Analog Line Ports AOUT2 BOUT2 AIN2 BIN2 AOUT3 BOUT3 AIN3 BIN3 AOUT1 BOUT1 AIN1 BIN1 AOUT4 BOUT4 AIN4 BIN4 +5.

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Full PDF Text Transcription

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ICs for Communications Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE PEB 24902 Version 1.1 PEF 24902 Version 1.1 Data Sheet 5.96 T2490-211-D2-7600 PEB 24902 Revision History Previous Releases: 2.96 p. 21/22 p. 24/25 p.26 p. 28 5.96 PLL characteristics Description of ADC and table 5, ADC Fig. 10 Description of DAC Edition 5.96 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
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