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IS450 - OPIC LIGHT DETECTOR WITH BULLT-IN SIGNAL PROCESSING CIRCULT FOR LIGHT MODULATION SYSTEM

Datasheet Summary

Description

The ICSI IS61SP12832 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors.

It is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Pentium™ or linear burst sequence control using MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin LQFP and 119-pin PBGA package.
  • Single +3.3V, +10%,.
  • 5% power supply.
  • Power-down snooze mode.

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Datasheet Details

Part number IS450
Manufacturer Sharp Electrionic Components
File Size 490.19 KB
Description OPIC LIGHT DETECTOR WITH BULLT-IN SIGNAL PROCESSING CIRCULT FOR LIGHT MODULATION SYSTEM
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Full PDF Text Transcription

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IS61SP12832 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin LQFP and 119-pin PBGA package • Single +3.3V, +10%, –5% power supply • Power-down snooze mode DESCRIPTION The ICSI IS61SP12832 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 131,072 words by 32 bits, fabricated with ICSI's advanced CMOS technology.
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