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LC322271T-70 - 2 MEG (131072 words X 16 bits) DRAM

Download the LC322271T-70 datasheet PDF. This datasheet also covers the LC3 variant, as both devices belong to the same 2 meg (131072 words x 16 bits) dram family and are provided as variant models within a single manufacturer datasheet.

Features

  • 131072 words × 16 bits configuration. Single 5 V ± 10% power supply. All input and output (I/O) TTL compatible. Supports fast page mode, read-modify-write and byte write. Supports output buffer control using early write and Output Enable (OE) control. 8 ms refresh using 512 refresh cycles. Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh. Follows the JEDEC 1 M DRAM (65536 words × 16 bits.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LC3-222.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Ordering number : EN*5085A CMOS LSI LC322271J, M, T-70/80 2 MEG (131072 words × 16 bits) DRAM Fast Page Mode, Byte Write Preliminary Overview The LC322271J, M and T is a CMOS dynamic RAM operating on a single 5 V power source and having a 131072 words × 16 bits configuration. Equipped with large capacity capabilities, high speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in a compact plastic package of SOJ 40-pin, SOP 40-pin, and TSOP 44-pin .
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