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SC32442B - RISC Microcontroller User Manual

General Description

section below.

Date Jan.

2005 Mar.

Key Features

  • with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the SC32442B minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SC32442B USER’S MANUAL Revision 1.2 NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, SOC Development Group, Ki-Heung, South Korea PRODUCT NAME: SC32442B RISC Microcontroller DOCUMENT NAME: SC32442B User's Manual, Revision 1.2 DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY: As a result of additional product testing and evaluation, some specifications published in the SC32442B User's Manual, Revision 1.2, have been changed. These changes are described in detail in the Revision Descriptions section below. DIRECTIONS: Please note the changes in your copy (copies) of the SC32442B User's Manual, Revision 1.2 or, simply attach the Revision Descriptions of the next page to SC32442B User's Manual, Revision 1.2 Revision 0.00 0.01 1.0 1.2 REVISION HISTORY Date Jan. 2005 Mar.