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S3P8849 - SAM87 family of 8-bit single-chip CMOS microcontrollers

Download the S3P8849 datasheet PDF. This datasheet also covers the S3P variant, as both devices belong to the same sam87 family of 8-bit single-chip cmos microcontrollers family and are provided as variant models within a single manufacturer datasheet.

Description

Table 1-1.

P0.3 Pin Type I/O Pin Description General I/O port (4-bit), configurable for digital input or n-channel open-drain, pushpull output.

Pins can withstand up to 5 V loads.

Features

  • include:.
  • Efficient register-oriented architecture.
  • Selectable CPU clock sources.
  • Release of Idle and Stop power-down modes by interrupt.
  • Built-in basic timer circuit with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels. S3C8847/C8849/P8849 MI.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (S3P-8849.pdf) that lists specifications for multiple related part numbers.

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Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
m o .c U 4 t e e h S a at PRODUCT OVERVIEW .D w SAM87 w PRODUCT FAMILY wSamsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide S3C8847/C8849/P8849 PRODUCT OVERVIEW 1 range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Release of Idle and Stop power-down modes by interrupt — Built-in basic timer circuit with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels.
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