Datasheet4U Logo Datasheet4U.com

S3C863A - 8-bit single-chip CMOS microcontroller

Description

Table 1-1.

P3.3 P3.4

P3.7 Pin Type I/O Pin Description General-purpose, 8-bit I/O port.

Features

  • are:.
  • Efficient register-oriented architecture.
  • Selectable CPU clock sources.
  • Idle and Stop power-down mode release by interrupt.
  • Built-in basic timer with watchdog function The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C8639/C863A/P863A.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
S3C831B 8-Bit CMOS Microcontroller Samsung Electronics
S3C852B 8-BIT CMOS MICROCONTROLLERS Samsung
S3C2412 32-BIT CMOS MICROCONTROLLER Samsung
S3C2412X 32-BIT CMOS MICROCONTROLLER Samsung
S3C2413X 32-BIT RISC MICROPROCESSOR Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
S3C8639 S3C8639/C863A/P863A MICROCONTROLLERS
S3C8639 8-bit single-chip CMOS microcontroller
S3C8615 S3C8618/C8615/P8615 MICROCONTROLLERS
S3C8618 S3C8618/C8615/P8615 MICROCONTROLLERS
S3C8625 S3C8625/C8627/C8629/P8629 MICROCONTROLLERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S3C8639/C863A/P863A PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.
Published: |