Datasheet4U Logo Datasheet4U.com

S3C820B - S3C-SERIES MICROCONTROLLERS

Description

Table 1-1.

P0.7 Pin Type I/O Pin Description I/O port with nibble-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; also configurable as external interface address lines A8

A15.

Features

  • include:.
  • Efficient register-oriented architecture.
  • Selectable CPU clock sources.
  • Idle and Stop power-down mode release by interrupt.
  • Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C820B.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
S3C831B 8-Bit CMOS Microcontroller Samsung Electronics
S3C852B 8-BIT CMOS MICROCONTROLLERS Samsung
S3C2412 32-BIT CMOS MICROCONTROLLER Samsung
S3C2412X 32-BIT CMOS MICROCONTROLLER Samsung
S3C2413X 32-BIT RISC MICROPROCESSOR Samsung

Other Datasheets by Samsung Semiconductor

Part Number Description
S3C821 S3C8-SERIES MICROCONTROLLES
S3C821A S3C8-SERIES MICROCONTROLLES
S3C8235 8-BIT CMOS MICROCONTROLLERS USERS MANUAL
S3C8238 8-BIT CMOS MICROCONTROLLERS USERS MANUAL
S3C8245 S3C8-SERIES MICROCONTROLLERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S3C820B PRODUCT OVERVIEW 1 PRODUCT OVERVIEW S3C-SERIES MICROCONTROLLERS Samsung’s S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.
Published: |