Datasheet Details
| Part number | K7S3218U4C |
|---|---|
| Manufacturer | Samsung Semiconductor |
| File Size | 478.89 KB |
| Description | 1Mx36 & 2Mx18 QDR II b4 SRAM |
| Datasheet |
 K7S3218U4C Datasheet
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General Description
Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs NOTE
Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC
Notes:
Data Outputs Write Control Pin,active when low Read Control Pin,active when low Block Write Control Pin,active when low Input Referenc
Key Features
- 1.8V+0.1V/-0.1V Power Supply.
- DLL circuitry for wide output data valid window and future frequency scaling.
- I/O Supply Voltage 1.5V+0.1V/-0.1V.
- Separate independent read and write data ports with concurrent read and write operation.
- HSTL I/O.
- Full data coherency, providing most current data.
- Synchronous pipeline read with self timed late write.
- Read latency: 2.5 clock cycles.
- Registered address, control and da.