Download the K7A161831B datasheet PDF.
This datasheet also covers the K7A163631B variant, as both devices belong to the same 18mb b-die sync sram specification 100tqfp with pb / pb-free family and are provided as variant models within a single manufacturer datasheet.
General Description
The K7A163631B and K7A161831B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.
Key Features
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 2.5 or 3.3V +/- 5% Power Supply.
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst.
Note: The manufacturer provides a single datasheet file (K7A163631B_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.
Full PDF Text Transcription for K7A161831B (Reference)
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K7A161831B. For precise diagrams, and layout, please refer to the original PDF.
K7A163631B K7A161831B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN T...
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cification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
K7A161831B Datasheet
