Datasheet Details
| Part number | K4X51323PC-7E |
|---|---|
| Manufacturer | Samsung Semiconductor |
| File Size | 287.19 KB |
| Description | 16M x32 Mobile-DDR SDRAM |
| Datasheet |
 K4X51323PC-7E Datasheet
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General Description
Clock : CK and CK are differential clock inputs.
All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK.
Internal clock signals are derived from CK/CK.
Key Features
- Mobile-DDR SDRAM.
- 1.8V power supply, 1.8V I/O power.
- Double-data-rate architecture; two data transfers per clock cycle.
- Bidirectional data strobe(DQS).
- Four banks operation.
- 1 /CS.
- 1 CKE.
- Differential clock inputs(CK and CK).
- MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver St.