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STL7N10F7 - N-channel Power MOSFET

Description

This device utilizes the 7 generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure.

The resulting Power MOSFET exhibits the lowest RDS(on) in all packages.

Table 1.

Features

  • 1 2 3 4 PowerFLAT™ 3.3x3.3 Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 76 5 G(4) Order code STL7N10F7 VDS 100 V RDS(on) max 0.035 Ω ID 7A.
  • N-channel enhancement mode.
  • Lower RDS(on) x area vs previous generation.
  • 100% avalanche rated.

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Full PDF Text Transcription

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STL7N10F7 N-channel 100 V, 0.027 Ω typ., 7 A STripFET™ VII DeepGATE™ Power MOSFET in a PowerFLAT™ 3.3x3.3 package Datasheet - production data Features 1 2 3 4 PowerFLAT™ 3.3x3.3 Figure 1. Internal schematic diagram D(5, 6, 7, 8) 8 76 5 G(4) Order code STL7N10F7 VDS 100 V RDS(on) max 0.035 Ω ID 7A • N-channel enhancement mode • Lower RDS(on) x area vs previous generation • 100% avalanche rated Applications • Switching applications Description th This device utilizes the 7 generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest RDS(on) in all packages. S(1, 2, 3) 1234 AM15810v1 Order code STL7N10F7 Table 1. Device summary Marking Package 7N10F PowerFLAT™ 3.3x3.
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